Multi-core processor - PDFSEARCH.IO - Document Search Engine

Multi-core processor
Results: 1324

#	Item
591	Licensing Oracle Software in the Cloud Computing Environment Add to Reading List Source URL: www.oracle.com Language: English Cross-platform software Oracle Database Cloud infrastructure Web services Oracle Corporation Amazon Elastic Compute Cloud Oracle Linux Virtualization software licensing Multi-core processor Cloud computing Computing Software
592	EVAL: Utilizing Processors with Variation-Induced Timing Errors∗ Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iac Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-09-13 00:20:01 Computer architecture Microprocessors Central processing unit Digital signal processing Fuzzy control system Multi-core processor Control system CPU cache Control theory Computer hardware Computing Control engineering
593	Scalable Cache Miss Handling for High Memory-Level Parallelism Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:12:53 Central processing unit Microprocessors Computer memory CPU cache Cache Runahead Multi-core processor Microarchitecture Memory-level parallelism Computer hardware Computer architecture Computing
594	CONCURRENCY AND COMPUTATION: PRACTICE AND EXPERIENCE Concurrency Computat.: Pract. Exper. 2014; 26:2386–2404 Published online 4 July 2014 in Wiley Online Library (wileyonlinelibrary.com). DOI: cpe.3304 SPECIAL Add to Reading List Source URL: blogs.oracle.com Language: English - Date: 2015-04-01 12:33:54 Concurrent computing Non-blocking algorithm Compare-and-swap Linearizability Lock Thread Concurrent data structure Multi-core processor Parallel computing Concurrency control Computing Concurrency
595	Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware∗ Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas University of Illinois at Urbana-Champaign {sarangi,atiwari,tor Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:11:09 Microprocessors Central processing unit X86 architecture Multi-core processor Parallel computing Athlon CPU cache P5 Microcode Computer hardware Computer architecture Computing
596	Understanding application performance via micro-benchmarks on three large supercomputers: Intrepid, Ranger and Jaguar Abhinav Bhatelé, Lukasz Wesolowski, Eric Bohm, Edgar Solomonik and Laxmikant V. Kalé Department of C Add to Reading List Source URL: charm.cs.illinois.edu Language: English - Date: 2011-05-01 22:22:28 Parallel computing Computer memory Jaguar Memory bandwidth Opteron CPU cache Blue Gene Multi-core processor Cray XT5 Computing Computer hardware Supercomputers
597	[3B2-9] mmi2013040006.3d[removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-09-18 22:48:13 Telecommunications engineering Computing Digital electronics Computer architecture Multi-core processor Parallel computing Very-large-scale integration CJON-DT Electronic engineering Electronics Microprocessors
598	Supercomputing the Climate Dr. Phil Webster Chief, Computational and Information Sciences and Technology Office NASA Goddard Space Flight Center Add to Reading List Source URL: www.nccs.nasa.gov Language: English - Date: 2014-02-26 14:29:10 Parallel computing Supercomputers GPGPU Video cards Intel Core Xeon Intel MIC FLOPS Multi-core processor Computing Computer hardware Computer architecture
599	A Framework for Dynamic Energy Efficiency and Temperature Management Michael Huang , Jose Renau , Seung-Moon Yoo , and Josep Torrellas Department of Computer Science Department of Electrical and Computer Engineering Univ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 12:19:17 Cache Central processing unit Computer architecture Microprocessors CPU cache Multi-core processor Parallel computing Dynamic random-access memory Computer hardware Computing Computer memory
600	VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages ‡ Ulya R. Karpuzcu∗ , Krishna B. Kolluru† , Nam Sung Kim† , and Josep Torr Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2012-04-21 17:10:28 Computing Computer memory Computer architecture Microprocessors Multi-core processor Parallel computing IC power supply pin MOSFET Random-access memory Integrated circuits Electronic engineering Electronics

UPDATE